
Serial Output Specification
SmartPrecision 3500Si Interpolator Operation
Page 13
Standard Communication Mode
Asserting the n_spiEnable signal freezes the current position word buffer and status information within the interpolator. The serial data is valid
50ns after the assertion of n_spiEnable signal. The n_spiEnable signal is kept asserted while spiClock signal toggles out the data.
Each serial data bit is valid on the falling edge of the clock signal. A high to low transition of the n_spiEnable signal must be accomplished
between acquisitions to allow the internal serial data buffer to update with new information.
Communication Mode Timing
Symbol Parameter Minimum Maximum Units
tspiH spiClockIn High Time 25 * ns
tspiL spiClockIn Low Time 25 * ns
tCSD n_spiEnable to DataValid 50 ns
tV
↓spiClockIn to Data Valid
25 ns
tCCS spiClockIn to n_spiEnable 0 ns
tCS n_spiEnable High 50 ns
tDNA n_spiEnable to HiZ 50 ns
*Assuming no propagation delay from user’s electronics and cabling. Please refer to page 16 for details.
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